Manuscripts

Recent Papers

Research Paper

Automation of UI design testing using Machine Learning

The buzz around SDLC and the ever-increasing need for testing each analytical component of a software component has incurred time losses in the entire cycle. The flaws in the design of any UI hurt the presentation and ease of access to users. Manually testing these entities might end up adding complexity, manual errors and unnecessary duration. Taking into consideration the dynamic elements of UI, this work presents a study on how the testing of these design elements can be carried out using different methods. It also addresses the technical challenges in the tasks carried out for the detection of objects and widgets in these dynamic interfaces. Motivated by machine learning concepts like Regions of Interests this work sheds light on the limitations and highlights of these methods.

Published by: Divya Gupta, Jagannath Aghav, Ashwini Chaudhari

Author: Divya Gupta

Paper ID: V7I3-1699

Paper Status: removed

Submitted: June 8, 2021

Full Details Track Status
Review Paper

Simple Borders Creating National Complexities

National borders are lines that separate one nation’s physical area from another nation. These borders usually help out in distinct identification of the nation’s location and prevent misunderstanding of the ownership of a piece of land or a distinct location. Most of the times, the airspace, land borders and coastlines are exploited by neighbours to create new crisis for capturing national boundaries. The extreme terrains present in the Indo Pakistan and Indo Bangladesh borders are dense sites of illegal activities like smuggling and, illegal drugs, weapons and human trafficking. The borders shared by India with Pakistan and Myanmar are hotspots of terrorism and cross border attacks for land capturing. The Indo Bangladesh borders has areas of high political sensitivity as there are many misunderstandings and problems related to ownership of a particular area. This paper discusses about the Indian border issues and existing solutions to solve these complexities and future solutions to resolve these issues.

Published by: M. D. Sabarinath

Author: M. D. Sabarinath

Paper ID: V7I3-1698

Paper Status: published

Published: June 8, 2021

Full Details
Research Paper

Costing and Rate Analysis of GFRG And Conventional Structure

This research paper is about costing and rate analysis of GFRG structure and conventional structure. Being an engineer is our first priority calling for solutions that work for our customers. Increasingly prices, housing is affordable at current rates technology which is why we needed to explore other types of construction plans to reduce construction costs. This paper an effort made to give an idea of how we can do that reducing construction costs and reducing construction time uses pre-design technology. GFRG construction technology also known as Rapid wall construction technology in India. Glass reinforced with gypsum panels, as they are ready-made gypsum building panels have empty holes. This is Rapid wall employed in residential and commercial buildings-built institutions. GFRG walls can be used as part of the structure such as walls and slabs, without outer columns and beams are required.

Published by: Snehal Ashok Salvi, Janhavi Deshpande, Vishal Jadhav, Nandini Pate, Vaishali Kamade, Aniruddha Chavan

Author: Snehal Ashok Salvi

Paper ID: V7I3-1725

Paper Status: published

Published: June 8, 2021

Full Details
Research Paper

64-bit Vedic multiplier with modified architecture and improved performance using Verilog

Vedic Maths is the ancient system of Indian mathematics. It has been extracted from 16sutras. Out of these 16 sutras, only one of these sutras named Urdhva Tiryagbhyam is used in this project. Urdhva is meant for Vertical and Tiryagbhyam is meant for the Crosswise multiplication process. This project is about designing of 8-, 16-, 32-, 64-bit Vedic multiplier with modified architecture and improved performance in comparison with a recent journal on 32-bit Vedic multiplier. And also 64-bit Vedic multiplier according to the reference journal is designed. The design of the proposed 64-bit Vedic multiplier consists of three stages, the first stage consists of four 32-bit Vedic multipliers, second stage has 96-bitcarry save adder and 95-bit modified carry skip adder in which internal stages consists of 8-bit and 16-bit Sklansky adders. and this design is implemented in XilinxISE14.7 and obtained a delay of 19.707ns, number of Slice LUT’s of 6989, power consumption of 111mW. The selected device in Xilinx14.7ISE is xc7k70t-3fbg484 from the Kintex-7 family. And also the reference design(64-bit Vedic multiplier) is calibrated using XilinxISE14.7 with the same device and obtained a delay of 36.630ns, number of Slice LUT’s of 8113, power consumption of 115mW.

Published by: Madhabhatthula Prem Kumar, Shiva Nand Singh

Author: Madhabhatthula Prem Kumar

Paper ID: V7I3-1707

Paper Status: published

Published: June 8, 2021

Full Details
Others

Detection and identification of high-quality cereals

Agricultural product grading is helpful in assessing the quality of a product and classifying it into categories. Presently, the grade analysis procedures involve the manual analysis of grains which is highly subjective and is influenced by human factors and the working environment. Thus, determining the quality of grains is a big challenge. In this paper, we have proposed a system that determines the quality of grains using image processing techniques. A variety of approaches were utilized to automate the screening process through machine vision approaches. Initially, the grain samples run on the conveyor belt, and then random images of grains are captured by the camera. The image processing algorithm is applied to the grain samples through MATLAB. Quality analysis of rice grains is determined by morphological features of rice grains. Various standards and procedures are then used to determine grades for the sample under test. The process of grading helps farmers to get the value for their produce, particularly rice, depending upon the results of quality inspections. Deep learning and machine learning models involving image processing has been tried in this paper to observe the computational accuracy

Published by: Aiswarya K.

Author: Aiswarya K.

Paper ID: V7I3-1694

Paper Status: published

Published: June 7, 2021

Full Details
Review Paper

A Practical approach for Firmware Reverse Engineering

Embedded products have become widely used entities in the network of households and enterprises. The exponential increment in its use has resulted in a lapse in security measures taken while building these products, leaving them vulnerable to security attacks. An important feature is that embedded devices work on what is commonly known as Firmware, Firmware, a piece of software that helps the embedded devices to work on the shared task. Securing the firmware will be an important step in securing the embedded product setup. To secure the firmware one needs to understand how the firmware works. One way to do so is to reverse engineering. Through reverse engineering, one can attempt to understand the device architecture, functionality, and potential vulnerabilities present in the device. A better understanding of the firmware implementation also helps in adding features if needed. This project aims to apply several types of reverse engineering techniques to increase the efficiency of reverse-engineering the firmware and find the vulnerabilities in a firmware-based setup. Also, estimate the level of damage the identified vulnerabilities can cause through rigorous penetration testing.

Published by: Akash C. Koturwar, Dr. V. K. Pachghare, Sharad Hange

Author: Akash C. Koturwar

Paper ID: V7I3-1488

Paper Status: published

Published: June 7, 2021

Full Details